1. Field of the Invention
The present invention relates to a digital signal processing system for digital signal transmission with scrambling/de-scrambling function.
2. Description of the Background Art
FIG. 25 is a circuit diagram of a conventional scrambling circuit for scrambling/de-scrambling digital signals in a digital signal processing system.
The scrambling circuit incudes a quasi-random code generator circuit 4 and an exclusive-OR gate 6, as shown in FIG. 25. The quasi-random code generator circuit 4 includes n D flip-flops FF1 to FFn (n.gtoreq.2) and (n-1) exclusive-OR gates EX1 to EX(n-1).
The D-input of the D flip-flop FF1 is connected to the Q-output of the D flip-flop FFn. The Q-output of the D flip-flop FFi (i=1 to (n-1)) is applied to a first input of the exclusive-OR gate EXi, and the output of the exclusive-OR gate EXi is applied to the D-input of the D flip-flop FF(i+1). The Q-output of the D flip-flop FFn is applied to a second input of the exclusive-OR gate EXi in common. A clock signal CLK is applied to the respective T-input of the D flip-flops FF1 to FFn through a clock input terminal 20 in common.
The quasi-random code generator circuit 4 in which the plurality of D flip-flops FF are connected in series, with the exclusive-OR gates EX provided respectively between the adjacent D flip-flops FF, outputs a quasi-random code RP based on a predetermined generator polynomial from the Q-output of the D flip-flop FFn. The generator polynomial is determined uniquely by the number of connected D flip-flops FF, the number of exclusive-OR gates EX and the positions of the exclusive-OR gates EX.
The exclusive-OR gate 6 has a first input receiving an input digital signal DI through a data input terminal 30 and a second input receiving the Q-output of the D flip-flop FFn. The exclusive-OR gate 6 outputs an output digital signal DO through a data output terminal 40.
FIG. 26 illustrates an exemplary data frame of packet data to be transmitted and received. The packet data contains start/end flags F, (real) data, and an abort pattern, as shown in FIG. 26.
The scrambling of the scrambling circuit of FIG. 25 will be described below. The D flip-flops FF1 to FFn are made to shift and to hold predetermined data as initial values for initialization. One of the D flip-flops FF1 to FFn is designed to hold "1".
For transmission of the packet including the data frame shown in FIG. 26, the inputted data pattern ((real) data, start/end flags, abort pattern) is accepted in the form of the input digital signal DI from the data input terminal 30. On detection of the start flag by a start flag detector not shown, scrambling is performed on the information following the start flag in the-input digital signal DI.
The scrambling will be discussed below. The input digital signal DI is given from the data input terminal 30. The exclusive-OR gate 6 calculates the exclusive-OR of the input digital signal DI and the Q-output of the D flip-flop FFn which is the quasi-random code for each bit to scramble the input digital signal DI. The exclusive-OR gate 6 then outputs the output digital signal DO.
For receiving the scrambled packet data, the inputted data pattern is accepted in the form of the input digital signal DI from the data input terminal 30. On detection of the start flag by the start flag detector not shown, de-scrambling is performed on the information following the start flag in the input digital signal DI.
The de-scrambling will be discussed below. The input digital signal DI is given from the data input terminal 30. The exclusive-OR gate 6 calculates the exclusive-OR of the input digital signal DI and the Q-output of the D flip-flop FFn which is the quasi-random code RP for each bit to de-scramble the input digital signal DI. The exclusive-OR gate 6 then outputs the output digital signal DO.
The scrambling (de-scrambling) is terminated by resetting the quasi-random code generator circuit 4 on detection of the abort pattern in the packet data frame by an abort pattern detector not shown. The scrambling circuit of FIG. 26 is designed to scramble/de-scramble the information between the data following the start flag and the abort pattern in the packet data.
The scrambling circuit (de-scrambling circuit) of the conventional digital signal processing system as above constructed presents the problem that a fixed generator polynomial of the quasi-random code generator circuit allows the scrambled digital signal to be readily decoded.